STC12C5A60S2

STC12C5A60S2 is a single-chip microcontroller based on a high performance 1T architecture 80C51 CPU, which is produced by STC MCU Limited. With the enhanced kernel, STC12C5A60S2 executes instructions in 1~6 clock cycles (about 6~7 times the rate of a standard 8051 device), and has a fully compatible instruction set with industrial-standard 80C51 series microcontroller. In-System Programming (ISP) and In-ApplicationProgramming (IAP) support the users to upgrade the program and data in system. ISP allows the user to download new code without removing the microcontroller from the actual end product; IAP means that the device can write non-valatile data in Flash memory while the application program is running. The STC12C5A60S2 retains all features of the standard 80C51. In addition, the STC12C5A60S2 has two extra I/O ports (P4 and P5), a 10-sources, 4-priority-level interrupt structure, 10-bit ADC, two UARTs, on-chip crystal oscillator, a 2-channel PCA and PWM, SPI, a one-time enabled Watchdog Timer.

Technical Specification

• Core Size 8-Bit
• Program Memory Type FLASH
• Core Processor 8051
• Speed 35MHz
• Voltage - Supply (Vcc/Vdd) 4V ~ 5.5V
• Program Memory Size 60KB
• RAM Size 1280Bytes
• EEPROM Size 1KB
• Number of I/O 44
• A/D 8x10bit
• D/A 2X8bit
• PWM 2
• UART/USART 2
• SPI 1